During the serial transmission of random data streams the number of data transitions from one to zero and zero to one, respectively, is not constant when counted over a given number of transmitted bits. This results in a variation of the bit transition density, which depends on what type of line code is used, e.g. 8B10B, scrambling, 10 Gb Ethernet etc. The bit-transition-density-variation ranges from three guaranteed transitions in ten bits to one transition only for more than 100 transmitted bits.
To resample a clock on which the data stream is based, clock data recovery systems are used. Conventional clock data recovery systems are generating a control loop error signal from the measurement of timing of when a transition in the incoming data signal stream occurs. This information is used to speed up or slow down the local resampling clock.
The bandwidth of a clock-data-recovery system is determined by the number of update measurements divided by the measurement interval. Even though serial data is usually transmitted in a balanced form (e.g. same number of ones and zeros and constant transition over a long time period) the short-term transition density and therefore the loop-update density may vary considerably. Therefore the gain and the bandwidth of the clock data recovery system loop is also varying and not well predictable.
From U.S. Pat. No. 5,896,067 a clock data recovery system is known wherein a clock signal is resampled from a signal having variations in the bit rate. The clock-data-recovery system includes a phase lock loop for recovering a bit clock from an incoming signal stream and means for resetting the output frequency of the phase lock loop to a preset value if that phase lock loop loses its lock or if adverse conditions are detected.
The disadvantage of that clock-data-recovery system lies in an insufficient accuracy of the resampled clock related to the incoming data signal stream, especially when the bit transition rate of the incoming signal stream is low. The loop may be reset onto a predetermined frequency if the phase lock loop of the clock-data-recovery system loses its lock. This may result in a continuous restarting of adjusting the frequency of the phase lock loop onto the incoming data signal stream. Thus the adjusting of the frequency may continuously restart from the preset frequency value that effectively differs from a frequency of a resampled clock optimized to the incoming signal stream.